1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a pumping voltage generating circuit and a semiconductor memory apparatus using the same.
2. Related Art
FIG. 1 is a schematic circuit diagram of a conventional pumping voltage generating circuit of a semiconductor memory apparatus. In FIG. 1, a pumping voltage generating circuit 1 of a semiconductor memory apparatus includes a first pump capacitor pump_cap1, a second pump capacitor pump_cap2, a first transistor N1, a second transistor N2, and a third transistor N3.
The first pump capacitor pump_cap1 performs a pumping operation in response to a first oscillation signal ‘osc1’, and the second pump capacitor pump_cap2 performs a pumping operation in response to a second oscillation signal ‘osc2’.
The first transistor N1 transfers an external power supply voltage VDD to a first node (node_A) in response to a first transfer signal ‘trans1’, and the second transistor N2 connects the first node (node_A) to a second node (node_B) in response to a second transfer signal ‘trans2’. In addition, the third transistor N3 connects the second node (node_B) to an output node (node_out) in response to a third transfer signal ‘trans3’. Here, an output of the output node (node_out) forms the pumping voltage VPP.
During operation of the pumping voltage generating circuit 1, when the first transfer signal ‘trans1’ is enabled, the first transistor N1 is turned ON so that the voltage level on the first node (node_A) increases up to the external power supply voltage VDD. When the voltage level of the first node (node_A) becomes the voltage level of the external power supply voltage VDD level, the first transfer signal ‘trans1’ is disabled. Then, the first transistor N1 is turned OFF.
Next, when the first transistor N1 is turned OFF, the first oscillation signal ‘osc1’ is transitioned from a ground voltage level to the external power supply voltage VDD level. The first pump capacitor pump_cap1 carries out the pumping operation at a rising timing of the first oscillation signal ‘osc1’ and increases the voltage level on the first node (node_A). Here, the voltage level on the first node (node_A) is ideally twice as much as that of the external power supply voltage VDD.
Then, if the voltage level of the first node (node_A) is twice as much as that of the external power supply voltage VDD, then the second transfer signal ‘trans2’ is enabled and the second transistor N2 is turned ON. Next, when the second transistor N2 is turned ON, the voltage level of the second node (node_B) is twice as much as the voltage level of the external power supply voltage VDD because the first node (node_A) is connected to the second (node_B). If the voltage level of the second node (node_B) is twice as much as the voltage level of the external power supply voltage VDD, then the second transfer signal ‘trans2’ is disabled and the second transistor N2 is turned OFF.
When the second transistor N2 is turned OFF, the second oscillation signal ‘osc2’ is transitioned from the ground voltage level to the external power supply voltage VDD level. The second pump capacitor pump_cap2 carries out the pumping operation at a rising timing of the second oscillation signal ‘osc2’ and increases the voltage level on the second node (node_B). Here, the voltage level on the second node (node_B) is ideally three times as much as the voltage level of the external power supply voltage VDD.
If the voltage level of the second node (node_B) is three times as much as the voltage level of the external power supply voltage VDD, then the third transfer signal ‘trans3’ is enabled and the third transistor N3 is turned ON. When the third transistor N3 is turned ON, the voltage level of the output node (node_out) is three times as much as the voltage level of the external power supply voltage VDD because the second node (node_B) is connected to the output node (node_out). As a result, the voltage level of the output node (node_out) is output as the pumping voltage VPP.
In general, the efficiency of the pumping voltage generating circuit 1 is determined by a ratio of an amount of current consumed in the first and second pump capacitors pump_cap1 and pump_cap2 to the voltage increment of the first to second nodes (node_A) and (node_B)
A large-sized pump capacitor can be used to increase the efficiency of the pumping voltage generating circuit 1. However, this increment of the capacitor size reduces the area efficiency of the semiconductor memory apparatus and increases the current consumption of the apparatus. Accordingly, it is necessary to improve the efficiency of the pumping voltage generating circuit 1 to implement the low-power semiconductor memory apparatus.